- 用途：用来关断clock信号的，主要是节省功耗
- 在什么阶段添加？
- RTL阶段：实现某种功能
- DC阶段：某些FF具有共同的特性，DC阶段会添加clock gating cell使这些特性起作用
- 结构：
- 最简单的可以用一个AND作为clock gating的cell（易产生glitch问题）
- Integrated gated clock cell (low level sensitive latch / downstrream triggerd FF will enable stable Q out put eventhough there is glitch in input D pin)
- XOR based clock enable cell
- 最简单的可以用一个AND作为clock gating的cell（易产生glitch问题）
- What is power gating and clock gating?
- Power and clock gating are two different techniques to reduce the overall power consumption within the SoC/ASIC. While clock gating focuses on the dynamic power of the circuit by reducing the switching frequency, the power gating focuses on the static/leakage power of the circuit by reducing the flow of current through the circuit.
- reg to clock gating的timing为何难修？
- 因为，clock gating cell 的clock 端默认是through pin，CTS时会平衡Reg 1和Reg2 （T1 = T2+T3)，但是check timing从reg1到ICG的ck端，capture path T2本就小于launch path T1,在加上T4,更难修了
- 方法：
- ICG一般靠近source，后面会加很多fanout，缩短Launch path是最好的选择。可以设置Reg1/CK为floating pin
- 将ICG设置单独的skew group，不与其它cell进行平衡
- 后端对CGC的处理：
- place阶段：将CGC尽可能往后放，place里面有个设置使clock gating cell aware
- CTS：
- CGC一般后面都会加很多fanout，CTS阶段会clone和declone clock gating cell